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Category : Verilog

Zynq7020 Flyby topology DDR3 Memory Test Results

Two and a half years ago, I drew my first flyby ddr3 memory layout when I first came into contact with high-speed PCBs. Later, although I have debugged many DDR3/DDR4 designs, I never tested this board that was already assembled. One reason is that the JTAG pin headers reserved are 1.27mm, making debugging inconvenient. Another reason is that this hardware needs several modifications to run normally. Finally, I got around to testing it, and here are the results: Read more

AlanCui's Avatar VerilogHighspeedLayout

A RV32I 5-stages Pipelined Processor

The processor uses a simplified AHB as the interface, and presents itself as a Harvard architecture. The implemented RISC-V subset only includes I, and does not support non-word-wided Load/Store operations. The entire execution flow is divided into five stages: IF/ID/OF/EX/MWB, which stands for: instruction fetch, decode, operand fetch (whether it’s an immediate or register), branch instruction predictional bypass, memory register write back. This division is made to ensure that the size occupied by each stage remains as balanced as possible. Due to the non-sequential transmission characteristics of the AHB bus, the instruction fetch will at least occupy one cycle of idle time, hence this processor can process an arithmetic instruction every two cycles and a memory access instruction every four cycles. Read more

AlanCui's Avatar Verilog