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Using the EmoePulse Avalanche Fast-Edge Generator to Generate True Random Numbers

In today’s world, cryptography has become the foundation of most digital infrastructure. The randomness in private key generation is a crucial prerequisite for modern cryptographic systems. Recently, I was gifted an EmoePulse transistor avalanche fast-edge generator by friend. Although this generator is designed primarily for rise-time testing or TDR (Time Domain Reflectometry) measurements, the intrinsic noise from such transistors can also be effectively used to generate cryptographically secure true random numbers. The following describes how we can build a true random number generator with no post-processing based on this device. Read more

AlanCui's Avatar Cryptography

Build a Stratum 1 NTP Server using GNSS PPS Signal and chronyd

Recently, I bought a Wyse 5070 thin client and planned to turn it into an internal network comprehensive server. One of the goals is to set up a precise internal NTP server. Therefore, I used the existing GNSSDO’s PPS signal output through RS-232 DCD input to the thin client and used it as a PPS signal source to tame chronyd. The date and time information can be obtained either via NEMA messages or other NTP servers. Read more

AlanCui's Avatar Time&Frequency

Narrowband 1:8 10MHz Reference Clock Distribution Amplifier

With the increasing number of time and frequency instruments in the laboratory, the two 10MHz reference outputs built into the GNSSDO are no longer sufficient for simultaneous operation. Therefore, a 1:8 10MHz clock distribution amplifier was designed and fabricated. Thanks to @滚筒洗衣机 for soldering most of the circuitry; this design is partly derived from the SRS FS730. Read more

AlanCui's Avatar Time&Frequency

Construct an USB488 instrument with TinyUSB and scpi-parser on ESP32

IEEE 488, as well GP-IB, is an actual standard of communication and controling in electrical test and measuring devices, USB TMC USB488 device class implements multiple characters which IEEE 488 have. We are going to support following capabilities on ESP32: All MANDATORY SCPI SR1 - Support for SRQ DT1 - Support for device trigger RL0 - Not support for Local/Remote operations, this device designed to accept commands from an queue, there is no need for switching between two modes. Also, TinyUSB not supports that. Read more

AlanCui's Avatar EmbeddedTest&Measure

Zynq7020 Flyby topology DDR3 Memory Test Results

Two and a half years ago, I drew my first flyby ddr3 memory layout when I first came into contact with high-speed PCBs. Later, although I have debugged many DDR3/DDR4 designs, I never tested this board that was already assembled. One reason is that the JTAG pin headers reserved are 1.27mm, making debugging inconvenient. Another reason is that this hardware needs several modifications to run normally. Finally, I got around to testing it, and here are the results: Read more

AlanCui's Avatar VerilogHighspeedLayout

Linear Power Supply with Switching Pre-Regulator

The OPA2189 is used as the main control operational amplifier, and the LM339 is used as the OVP/OCP/OTP protection comparator. Diodes are used to combine the CV/CC loop. Simulated crossover frequencies are 190kHz/100kHz. The output stage uses four parallel TIP41C transistors in conjunction with an 8050 as a Darlington output stage to reduce amplifier’s current load. Read more

AlanCui's Avatar PowerSupply

A RV32I 5-stages Pipelined Processor

The processor uses a simplified AHB as the interface, and presents itself as a Harvard architecture. The implemented RISC-V subset only includes I, and does not support non-word-wided Load/Store operations. The entire execution flow is divided into five stages: IF/ID/OF/EX/MWB, which stands for: instruction fetch, decode, operand fetch (whether it’s an immediate or register), branch instruction predictional bypass, memory register write back. This division is made to ensure that the size occupied by each stage remains as balanced as possible. Due to the non-sequential transmission characteristics of the AHB bus, the instruction fetch will at least occupy one cycle of idle time, hence this processor can process an arithmetic instruction every two cycles and a memory access instruction every four cycles. Read more

AlanCui's Avatar Verilog